ZYNQ 7020 Minimum System FPGA XILINX ( Smart Zynq SL Original ) XC7Z020-CLG484 Development board

Hardware version V1.3B (with pin headers, not soldered) adds a 40-pin RGB LCD screen cable interface

https://ko.aliexpress.com/item/1005010651628580.html?gatewayAdapt=glo2kor

Update Log:

V1.3B, March 13, 2026

Adjustments:

1. On the basis of the V1.3 version, a 40-pin RGBLCD interface (in FPC connector form, compatible with the RGB screen of Point Zero Atom, including 35 FPGA IO ports) was added.

2. The remaining size functions are exactly the same as the V1.3 version.

V1.3 Version Description: October 2024

Reason for Adjustment: To make the row pins on both sides of the motherboard compatible with the external modules designed by our store in the future, this hardware has been slightly adjusted and updated.

1. The power position of the row pins on one side was adjusted (as shown in the following block diagram) (V1.3 and V1.2 are consistent and mutually compatible, and no longer compatible with V1.1 version)

2. The model of the TI power supply chip was adjusted (it was also a TI power supply chip before, and it had no impact on the usage)

3. The CLK pin of HDMI when I is the SRCC clock pin was adjusted (can adapt to more third-party HDMI IP cores) (V1.3 changed from V1.2)

The version information can be found on the board label (near the POR button)

ZYNQ 7020 Minimum System Development board

Board resources

1. The main chip ZYNQ has been upgraded to 7020(new industrial-grade chip)

2.512MB DDR3 (4Gbit)

3. TF Card slot (responsible for TF boot)

4. 128Mbit (16MB) QSPI FLASH (capable of booting)

5. One EEPROM 2KB(PL)

6. Two-channel LED lights (PL

7. Two buttons (PL) + one button for resetting the control system POR

8. One UART (PL) Type-C interface

9. 68 GPIOs (all led out from the PL terminal) (34 groups) are all connected in pairs through differential lines, with equal lengths within the differential lines

10. One side of the BANK is independently powered and the BANK voltage can be adjusted through a resistor

11. Gigabit Ethernet (connected to the PL end)

12.HDMI output interface

13.PL is connected to a 50M active crystal oscillator

Both HDMI and USB are connected to ESD electrostatic protection devices

It does not come with a downloader. An external xilinx downloader is required

The differences among the three boards: Smart Zynq SP2 (580), Smart Zynq SP (580), and Smart Zynq SL (380)

Smart Zynq SP2: Built-in USB downloader and 1.3-inch 240x240 resolution screen

Smart Zynq SP: Built-in USB downloader and 1.47-inch 320x172 resolution screen

Smart Zynq SL: Requires an external downloader without USB and screen

The remaining circuits are exactly the same for all three

The JTAG interface is as follows. It can be compatible with most 10-pin Xilinux downloaders with a spacing of 2.54mm from our store or other stores

Note: Some domestic downloader solutions may not be compatible with ZYNQ chips. Additionally, Altera's downloader is not universal

HELLOFPGA also has a new model of ZYNQ motherboard, LemonZYNQ (LemonZynq can directly run the official image of PYNQ)

HELLOFPGA has also newly launched a 5-inch IPS RGB screen, which can be directly compatible with the SmartZynqSL motherboard