AD9226 High-Speed 12-Bit ADC Module 65MSPS Dual-Channel, 130MSPS Single-Channel Data Acquisition Board for FPGA MCU Oscilloscope

AD9226 High-Speed 12-Bit ADC Data Acquisition Module, Dual-Channel 65M Single-Channel 130M Sampling

Product Introduction:

This module is built around the AD9226 chip, a monolithic, single-supply, 12-bit, 65 MSPS analog-to-digital converter (ADC) that integrates a high-performance sample-and-hold amplifier and a voltage reference. Operating on a single +5V power supply and featuring two onboard AD9226 chips, the module supports dual-channel 65 MSPS simultaneous acquisition or can be combined for single-channel 130 MSPS high-speed sampling. With a 50Ω input impedance, a wide ±5V (10 Vpp) input range, and a 350 MHz analog bandwidth, it guarantees precise acquisition of high-speed signals even at the maximum sampling rate. This module is widely suitable for applications such as sensor signal acquisition, high-speed data logging, communications, and laboratory instrumentation.

Features:

High Speed & High Precision: 12-bit resolution with sampling rates up to 65 MSPS per channel or 130 MSPS in combined mode.

Dual Operating Modes (selectable via jumper cap):

Dual-Channel Mode (65 MSPS per channel): Jumper set to B-C. Supports simultaneous acquisition and processing of two signal paths.

Single-Channel Mode (130 MSPS): Jumper set to A-B. Doubles the sampling rate for capturing extremely fast transient signals on a single channel.

Excellent Signal Fidelity: A 350 MHz analog bandwidth ensures accurate digitization of high-frequency signal components.

Robust & Reliable Design: Includes reverse polarity protection for the power supply, preventing damage from accidental misconnection.

Complete Development Support: Comes with Verilog reference code and a Quartus II 13.0 project file for quick integration and evaluation on FPGA platforms.

Technical Specifications:

Core Chip: AD9226

Module Type: High-Speed Analog-to-Digital Converter (ADC) Module

Power Supply: +5V DC (Do not exceed this voltage)

Sampling Rate: 65 MSPS or 130 MSPS (depending on operating mode)

Resolution: 12-bit

Input Voltage Range: ±5V (10 Vpp)

Input Impedance: 50Ω

Analog Bandwidth: 350 MHz

Number of Channels: 2 physical channels

Operating Modes:

Jumper A-B: Single-Channel 130 MSPS mode (uses INA input)

Jumper B-C: Dual-Channel 65 MSPS mode

Reference Voltage: Internal 2V

Data Output Format: Straight binary code

Control Signal Level: 3.3V (compatible with most FPGAs and MCUs)

Example Code & Platform: Verilog HDL, Quartus II 13.0

Output Mode: Parallel data

Input Interface: SMA connector

Output Interface: 2.54mm pitch female header

Power Interface: 2.54mm pitch terminal block (default) / header

Module Protection: Reverse polarity protection for power supply

Typical Applications: High-speed ADC acquisition, data acquisition systems, oscilloscope front-ends, software-defined radio (SDR), industrial measurement

Module Dimensions: 55mm x 33mm

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